Conventional EEPROMs typically employ three to four transistors, which include a tunnel diode device coupled to the floating gate of the sense transistor to charge the latter and a select or row transistor to activate the cell. The use of three or four transistors to realize a cell substantially limits the size reduction possible for EEPROM arrays. Furthermore, typical EEPROM cells require the application of voltages in excess of 15 volts. This therefore requires special processing to reduce leakage and a larger layout to avoid unwanted field transistor turn-on, i.e., the use of high voltage transistors typically have longer channel lengths, and therefore, significantly larger sizes. This is especially the case with respect to the row transistor, since high voltage is applied to the source during the ERASE mode. The peripheral driving circuitry also requires higher voltage transistors to handle these high voltage driving signals.
The row transistor for the memory cell is typically referred to as a "select" transistor that is utilized to isolate the memory cell from the Column or Bit Line. Further, when the row transistor is utilized in combination with an EEPROM cell of the Fowler-Nordheim type, the row transistor allows for a wide range of threshold voltages on the memory cell transistor. Typically, a memory cell transistor is comprised of a stacked confirmation wherein a floating gate is isolated from the channel region of the transistor by a thin layer of gate oxide with a thickness less than 100 .ANG.. A layer of interlevel oxide is then disposed over the surface of the floating gate and a then a control gate disposed over the interlevel oxide. During fabrication, these structures are formed with a double level poly process such that two layers of polycrystalline silicon are disposed on the substrate, separated by the interlevel oxide and then patterned and etched to define a stacked gate structure. In this structure, the lateral edges of the control gate are aligned with the lateral edges of the floating gate in a self-aligned gate process. Thereafter, the stacked gate structure is utilized to mask off a channel region during implanting of the source/drain regions. One disadvantage to the stacked gate structure is the control of its threshold voltage. During an ERASE operation, when the floating gate is positively charged, the threshold can actually go negative. If the row transistor were not utilized, this could cause unwanted conduction in non-selected rows. However, the threshold voltage of the row transistor, when disposed in parallel with the memory cell transistor, prevents this unwanted turn on since, when the gate of the row transistor is low, the row transistor will remain off, regardless of the conductivity of the memory cell transistor. However, one disadvantage to the utilization of the row transistor is the lack of symmetry in the array and the necessity for additional select lines for each row of memory cells and the use of a relatively high voltage transistor for the row transistor.